A data-centre GPU looks nothing like a CPU inside. One enormous die of repeated tiles sits between stacks of memory, on a slab of silicon that exists only to connect them.
Package
A logic die of roughly 800 mm² flanked by six stacks of high bandwidth memory, all mounted on a silicon interposer, then on a substrate with thousands of solder balls.
Die
No big cores. One small block, the streaming multiprocessor, repeated over a hundred times, with memory interfaces along the edges that face the memory.
One SM
Four near-identical columns: warp scheduler, register file, 16 integer and 16 floating-point lanes, and a tensor core, over a shared L1 cache.
Memory stack
DRAM dies thinned and stacked, drilled through with copper vias. This is the shortest, widest road from memory to logic that can currently be built, and it is still the bottleneck.
Package and memory figures are manufacturer specifications for an H100-class part. The die floorplan is illustrative; the SM layout follows NVIDIA's published block diagrams.