SYNAPSE is a proposed memory centric inference platform: a digital accelerator first, with analog, sparse and optical engines added only where they earn their cost.
One programming model, several engines
The host submits a model manifest and requests. The SAMANVAYA controller validates precision plans, reserves KV capacity and dispatches a dependency graph through explicit buffers and completion events.
The digital path is the correctness anchor
Tensor tiles run dense linear algebra; vector cores run reductions, normalisation, rotary embeddings and sampling. Any operation an optional engine cannot take falls back to a digital kernel.
Memory shared by address contract
A unified logical namespace, without fully coherent caches across chiplets. Buffers have owners, layouts and lifetimes; DMA completion and fences decide when another engine may read a result.
What would be the invention
Not the blocks, which are familiar, but a validated placement and precision policy, an efficient memory system and a model that exploits them. Extra engines must save more work than they create.
SYNAPSE Concept Architecture, technical concept study v1.0, 12 November 2026, section 4 and figure 1.